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How VLSI Chips Embed Resistors and Capacitors

Very Large Scale Integration Circuit, VLSI) is a type of integrated circuit that combines a large number of transistors into a single chip, with a higher integration level than large-scale integration circuits. The number of integrated transistors varies according to different standards. From the 1970s onwards, with the development of complex semiconductor and communication technologies, research and development on integrated circuits also gradually unfolded. The control core microprocessor in computers is the most typical example of a VLSI. VLSI design, especially digital integrated circuit design, usually employs electronic design automation methods and has become one of the important branches of computer engineering.


Resistance Design in VLSI Chips


It is not possible to use macroscopic components to realize circuits in VLSI chips like in PCBs, as all components of VLSI are integrated on silicon wafers, that is, through oxidation, photolithography, doping, and other processes on silicon to form complete circuits. The realization of circuit functions necessitates the use of resistors, capacitors, and inductors, which need to be constructed through different layers in the physical layout of the VLSI chip. Resistance is usually achieved through very long polysilicon bars, which are part of the VLSI physical layout. Sometimes, small width-to-length ratio (W/L) constantly conductive MOS transistors are also used to achieve resistance.


Capacitance Design in VLSI Chips


In VLSI chips, the design of capacitors requires understanding that an oxidation layer already exists between the gate and substrate of the MOS devices. This means that there will be parasitic capacitances whether in the active or field areas. These parasitic capacitances can be utilized in the design to build capacitors. For example, a simple method is to connect the source and drain of an MOS transistor as terminal a and use the gate as terminal b. Then the capacitance between a and b is given by K (dielectric constant of the oxidation layer) multiplied by (L*W). Another method is the PIP (Poly-Insulator-Poly) capacitor, which requires two layers of polysilicon processes, adding several more steps compared to single-layer polysilicon processes. The top and bottom plates of PIP capacitors are not interchangeable, and there are parasitic capacitances, but these can be minimized through layout design and process control. Another commonly used capacitor is the MOM (Metal-Oxide-Metal) capacitor, which will not be elaborated further here.


Inductor Design in VLSI Chips


In CMOS technology, one of the most widely used integrated inductors is the on-chip spiral inductor, realized on the chip as a planar inductor. The planar inductor can have circular, octagonal, square, and other shapes; due to design rules, the angles cannot be arbitrary, so square structures are most commonly used. The inductance value of on-chip spiral inductors is mainly determined by the number of turns, metal width, metal spacing, and diameter dimensions, while their parasitic capacitance and resistance are determined by both lateral and vertical dimensions. Generally, the highest metal layer is chosen for the inductor to reduce the oxide layer capacitance between the inductor and substrate. In CMOS technology, the top metal layer is always the thickest.


Manufacturing Methods for VLSI Chips


An integrated circuit with over 100,000 components or gates is called VLSI. VLSI was developed in the late 1970s and is primarily used in memory and microprocessor manufacturing. The 64k-bit random access memory was the first generation of VLSI, containing approximately 150,000 components with a line width of 3 microns. Today, VLSI integration has reached 6 million transistors with a line width of 0.3 microns.


VLSI chips use planar technology, with the manufacturing process roughly divided into four steps: oxidation, photolithography, doping, and deposition. First, a batch of very pure single crystal silicon is obtained. According to the doping requirements for IC substrates, a certain proportion of III/V group elements are added and then melted. Using the stretching growth method, a cylindrical low-doped silicon rod is pulled out, which is then cut and polished to obtain wafers. Processing begins with these wafers as the base.


First, a uniform oxidation layer is formed on the wafer surface, followed by the formation of a polysilicon gate according to the layout design. Photolithography is then used to etch away the oxidation layer in active regions to expose the substrate of the active area to the air. Next, ion implantation is used to dope the exposed active area to form the source and drain of MOS transistors. Aluminium is deposited in the active area to connect external circuits. This completes a simple MOS transistor.


In the manufacturing process, the doping of the substrate is controlled to be low to reduce its conductivity. At the active area, high doping is used to enhance conductivity and form an inversion channel. Thus, even though the substrate is not highly conductive, it forms a diode with the active area semiconductor, determining that CMOS circuits must have NMOS connected to GND and PMOS connected to VDD.

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